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integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 pin configuration recommended application: 48-pin lo w cost ck505 w/fully integ r ated vreg and ser ies resistors on differential outputs output features:? integrated series resistors on differential outputs ? 2 - cpu differential push-pull pairs ? 4 - src differential push-pull pairs ? 1 - cpu/src selectable differential push-pull pair ? 1 - src/dot selectable differential push-pull pair ? 1- src/stop_inputs selectable differential push-pull pair ? 1 - 25mhz se1 output for wake-on-lan applications ? 3 - pci, 33mhz ? 1 - usb, 48mhz ? 1 - ref , 14.31818mhz key specifications:? cpu outputs cycle-cycle jitter < 85ps ? src output cycle-cycle jitter < 125ps ? pci outputs cycle-cycle jitter < 250ps ? +/-100ppm frequency accuracy on all clocks 48-pin ck505 for intel systems advance information documents contain information on products in the formative or design phase development. characteristic data and other specifications are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. features/benefits:? supports spread spectrum modulation, default is 0.5%down spread ? uses external 14.318mhz crystal, external crystal loadcaps are required for frequency tuning not recommended f or ne w designs. the last time buy date for this product is 5/19/2011. please refer to pdn k-10-18. t ab le 1: cpu frequenc y select t ab le fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 1 1 1 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common outpu t parameters table for correct values. reserved 100.00 33.33 14.318 48.00 96.00 pci0/cr#_a 1 48 sclk vddpci 2 47 sdata pci4/src5_en 3 46 ref0/fslc/test_sel pci_f5/itp_en 4 45 vddref gndpci 5 44 x1 vdd48 6 43 x2 usb_48mhz/fsla 7 42 gndref gnd48 8 41 fslb/test_mode vdd96_io 9 40 ck_pwrgd/pd# dot96t_lpr/srct0_lpr 10 39 vddcpu dot96c_lpr/srcc0_lpr 11 38 cput0_lpr gnd 12 37 cpuc0_lpr vdd 13 36 gndcpu se1 14 35 cput1_lpr_f gnd 15 34 cpuc1_lpr_f srct2_lpr/satat_lpr 16 33 vddcpu_io srcc2_lpr/satac_lpr 17 32 cput2_itp_lpr/srct8_lpr gndsrc 18 31 cpuc2_itp_lpr/srcc8_lpr srct3_lpr/cr#_c 19 30 vddsrc_io srcc3_lpr/cr#_d 20 29 srct7_lpr/cr#_f vddsrc_io 21 28 srcc7_lpr/cr#_e srct4_lpr 22 27 gndsrc srcc4_lpr 23 26 vddsrc cpu_stop#/srcc5_lpr 24 25 pci_stop#/srct5_lpr 48-ssop/tssop * internal pull-up resistor ** internal pull-down resistor 9lprs535
2 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 ssop/tssop pin description pin # pin name type description 1 pci0/cr#_a i/o 3.3v pci clock output or cr#_a input. default is pc i0. to configure this pin as cr#_a, the pci output must first be disabled in byte 2, bit 0. byte 5, bit 7: 0 = pci0 enabled (default), 1= cr#_a enabled. byte 5, bit 6: 0 = cr#_a controls src0 (default), 1 = cr#_a# controls src2. 2 vddpci pwr power supply for pci clocks, nominal 3.3v 3 pci4/src5_en i/o 3.3v pci clock output / src5 enable strap. on power up, the logic value on this pin determines if src5 or cpu_stop#/pci_stop# is enabled. the latched value c ontrols the pin function as follows 0 = pci_stop#/cpu_stop# 1 = src5/src5# 4 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable s trap. this output is not affected by the state of t he pci_stop# pin. on powerup, the state of this pin determines whether p ins 38 and 39 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 5 gndpci pwr ground pin for the pci outputs 6 vdd48 pwr power pin for the 48mhz output.3.3v 7 usb_48mhz/fsla i/o 3.3v tolerant input for cpu frequency selection. re fer to input electrical characteristics for vil_fs and vih_fs values. / fixed 48mhz usb clock output. 3.3v. 8 gnd48 pwr ground pin for the 48mhz outputs 9 vdd96_io pwr power pin for the dot96 clocks, nominal 1.05v to 3.3v. 10 dot96t_lpr/srct0_lpr out true clock of push-pull src or dot96 with integrate d series resistor. no 50 ohm pull down needed. defa ult is srct0. after powerup, this pin function may be changed to dot96t via smbus byte 1, bit 7 as follows: 0= src0t 1=dot96t 11 dot96c_lpr/srcc0_lpr out complementary clock of push-pull src or dot96 with integrated series resistor. no 50 ohm pull down nee ded. default is src0c. after powerup, this pin function may be chan ged to dot96c via smbus byte 1, bit 7 as follows: 0= src0c 1=dot96c 12 gnd pwr ground pin. 13 vdd pwr power supply, nominal 3.3v 14 se1 out ck505 singled ended output 1. 3.3v. 15 gnd pwr ground pin. 16 srct2_lpr/satat_lpr out true clock of differential 0.8v push-pull src/sata output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 17 srcc2_lpr/satac_lpr out complementary clock of differential 0.8v push-pull src/sata output with integrated 33ohm series resis tor. no 50ohm resistor to gnd needed. 18 gndsrc pwr ground pin for the src outputs 19 srct3_lpr/cr#_c i/o true clock of push-pull src output with int. 33ohm series resistor/cr#_c input. disable src3 via byte 4, bit 7, before using as cr#_c. byte 5, bit 3: 0=src3 (default), 1=cr#_c. byte 5, bit 2: 0=cr#_c controls src0 (default), 1=c r#_c controls src2 20 srcc3_lpr/cr#_d i/o complementary clock of push-pull src output with in t. 33ohm series resistor/cr#_d input. disable src3 via byte 4, bit 7, before using as cr#_d. byte 5, bit 1: 0=src3 (default),1=cr#_d. byte 5, bit 0: 0=cr#_d controls n/a (default), 1=cr #_d controls src4 21 vddsrc_io pwr 1.05v to 3.3v from external power su pply 22 srct4_lpr out true clock of push-pull src output wi th int. 33ohm series resistor. 23 srcc4_lpr out complementary clock of push-pull src output with int. 33ohm series resistor. 24 cpu_stop#/srcc5_lpr i/o stops all cpuclk, except those set to be free runni ng clocks / complementary clock of push-pull src pair with int. 33ohm series resistor.
3 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 ssop/tssop pin description (continued) 25 pci_stop#/srct5_lpr i/o stops all pciclks at logic 0 level, when low. can also stop src clocks. free running pciclks are not effected by this input. / true clock of push-pull src pair with in t. 33ohm series resistor. 26 vddsrc pwr supply for src clocks, 3.3v nominal 27 gndsrc pwr ground pin for the src outputs 28 srcc7_lpr/cr#_e i/o complementary clock of push-pull src output with in t. 33ohm series resistor/cr#_e input. disable src7 via byte 3, bit 3 before using as cr#_e. byte 6, bit 7: 0=src7 (default), 1=cr#_e outputs controlled by cr#_e are not present on this device 29 srct7_lpr/cr#_f i/o true clock of push-pull src output with int. 33 ohm series resistor/cr#_f input. disable src7 via byte 3, bit 3 before using cr#_f. byte 6, bit 6: 0 = src7 (default),1 = cr#_f enabled to control src8. 30 vddsrc_io pwr 1.05v to 3.3v from external power su pply 31 cpuc2_itp_lpr/srcc8_lpr out complementary clock of low power differential cpu2_ itp/src pair. no rs needed. the function of this pi n is determined by the latched input value on pin 7, pcif5/itp_en o n powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 32 cput2_itp_lpr/srct8_lpr out true clock of low power differential cpu2_itp/src8 pair. no rs needed. the function of this pin is det ermined by the latched input value on pin 7, pcif5/itp_en on power up. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 33 vddcpu_io pwr 1.05v to 3.3v from external power su pply 34 cpuc1_lpr_f out complementary clock of differential pair 0.8v push- pull cpu outputs with integrated 33ohm series resis tor. free running during iamt. no 50ohm resistor to gnd needed. 35 cput1_lpr_f out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. fre e running during iamt no 50 ohm resistor to gnd needed. 36 gndcpu pwr ground pin for the cpu outputs 37 cpuc0_lpr out complementary clock of differential pair 0.8v push- pull cpu outputs with integrated 33ohm series resis tor. no 50 ohm resistor to gnd needed. 38 cput0_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 5 0 ohm resistor to gnd needed. 39 vddcpu pwr supply for cpu clocks, 3.3v nominal 40 ck_pwrgd/pd# in notifies ck505 to sample latched in puts, or iamt entry/exit, or pwrdwn# mode 41 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. r efer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi -z and ref/n divider mode while in test mode. refer to test clarification table. 42 gndref pwr ground pin for the ref outputs. 43 x2 out crystal output, nominally 14.318mhz 44 x1 in crystal input, nominally 14.318mhz. 45 vddref pwr ref, xtal power supply, nominal 3.3v 46 ref0/fslc/test_sel i/o 14.318 mhz reference clock./ 3.3v tolerant input fo r cpu frequency selection. refer to input electrica l characteristics for vil_fs and vih_fs values. /test_sel: 3-level latche d input to enable test mode. refer to test clarific ation table 47 sdata i/o data pin for smbus circuitry, 3.3v tolera nt. 48 sclk in clock pin of smbus circuitry, 5v tolerant.
4 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 ics9lprs535 is compliant to the intel ck505 y ello w co v er specification. this cloc k synthesiz er pro vides a single chip solution for intel desktop chipsets. ics9lprs535 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output f or ser ial a t a and pci-express suppor t. general descriptionblock diagram po wer gr oups description vdd gnd 33 36 cpu outputs 39 36 cpu/src analog 30, 21 18, 27 src outputs 13 15 pll3 25mhz 9 12 dot96 outputs 6 8 usb 48 output/analog 45 42 xtal, ref 2 5 pci outputs pin number ref cpu(1:0) cpu pll1 ss osc ref src(7,5:3) pll2 non-ss pll3 non-ss src8/itp pci(5:4,0) src2/sata se1 (25mhz) 25mhz sata dot96mhz pci33mhz s r c = s r c _ m a i n src0/dot96 48mhz 48mhz cpu fsla ckpwrgd/pd# pci_stop# cpu_stop# cr#_(a,c:d) src5_en itp_en fslc/testsel fslb/testmode control logic x1 x2
5 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 absolute maximum ratings - dc parameters parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 7 maximum supply voltage vddxxx_io low-voltage differen tial i/o supply 3.8 v 7 maximum input voltage v ih 3.3v inputs 4.6 v 4,5,7 minimum input voltage v il any input gnd - 0.5 v 4,7 storage temperature ts - -65 150 c 4,7 input esd protection esd prot human body model 2000 v 6, 7 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied , nor guaranteed. 3 maximum input voltage is not to exceed vdd ac electrical characteristics - low power different ial outputs parameter symbol conditions min max units notes rising edge slew rate tslr averaging on 2.5 4 v/ns 2, 3 falling edge slew rate tflr averaging on 2.5 4 v/ns 2, 3 slew rate variation tslvar averaging on 20 % 1, 10 differential voltage swing vswing averaging off 300 mv 2 crossing point voltage vxabs averaging off 300 550 mv 1,4 ,5 crossing point variation vxabsvar averaging off 140 mv 1,4,9 maximum output voltage vhigh averaging off 1150 mv 1,7 minimum output voltage vlow averaging off -300 mv 1,8 duty cycle dcyc averaging on 45 55 % 2 cpu[1:0] skew cpuskew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpuskew20 differential measurement 1 50 ps 1 src[10:0] skew srcskew differential measurement 3000 ps 1,6,11 1 measurement taken for single ended waveform on a co mponent test board (not in system) 2 measurement taken from differential waveform on a c omponent test board. (not in system) 3 slew rate emastured through v_swing voltage range c entered about differential zero 4 vcross is defined at the voltage where clock = cloc k#, measured on a component test board (not in syst em) 9 the total variation of all vcross measurements in any particular system. note this is a subset of v_ cross min/mas (v_cross absolute) allowed. the inte nt is to limit vcross induced modulation by setting c_cross_delta to be s maller than v_cross absolute 10 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured usin g a +/-75mv window centered on the average cross po int where clock rising meets clock# falling. the median cross point is us ed to calculate the voltage 11 for pcie gen2 compliant devices, src 3, 4, 6, and 7 will have 0 ps nominal skew. 5 only applies to the differential rising edge (clock rising, clock# falling) 6 total distributed intentional src to src skew. pc ie gen2 outputs (src3, 4, 6 and 7) will have 0 nomi nal skew. maximum allowable interpair skew is 150 ps. 7 the max voltage including overshoot. 8 the min voltage including undershoot. notes on dif output ac specs: (unless otherwise not ed, guaranteed by design and characterization, not 100% tested in production). electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 pp m 1,2 33.33mhz output no spread 29.99700 30.00300 ns 2 33.33mhz output spread 30.08421 30.23459 ns 2 33.33mhz output no spread 29.49700 30.50300 ns 2 33.33mhz output nominal/spread 29.56617 30.58421 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 pin to pin skew t skew v t = 1.5 v 250 ps 2 intential pci to pci delay t skew v t = 1.5 v 100 200 ps 2 duty cycle d t1 v t = 1.5 v 45 55 % 2 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 2 output low current i ol absolute min/max period t abs output high current i oh clock period t period
6 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 electrical characteristics - input/supply/common ou tput dc parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c supply voltage vddxxx supply voltage 3.135 3.465 v supply voltage vddxxx_io low-voltage differential i/o supply 0.9975 3.465 v 10 input high voltage v ihse single-ended 3.3v inputs 2 v dd + 0.3 v 3 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 3 low threshold input- high voltage v ih_fs_test 3.3 v +/-5% 2 vdd + 0.3 v 8 low threshold input- fsc = '1' voltage v ih_fs_fsc 3.3 v +/-5% 0.7 1.5 v 8 low threshold input- fsa,fsb = '1' voltage v ih_fs_fsab 3.3 v +/-5% 0.7 vdd+0.3 v low threshold input-low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 input leakage current i inres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 i ddop3.3 full active, c l = full load; idd 3.3v 125 ma i ddopio full active, c l = full load; idd io 50 ma 10 i ddiamt3.3 m1 mode, 3.3v rail 40 ma i ddiamtio m1 mode, io rail 10 ma i ddpd3.3 power down mode, 3.3v rail 5 ma i ddpdio power down mode, io rail 0.1 ma 10 input frequency f i v dd = 3.3 v 15 mhz pin inductance l pin 7 nh c in logic inputs 1.5 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tdrive_cr_off t drcroff output stop after cr deasserted 400 ns tdrive_cr_on t drcron output run after cr asserted 0 us tdrive_cpu t drsrc cpu output enable after pci_stop# de-assertion 10 ns tfall_se t fall 10 ns trise_se t rise 10 ns smbus voltage v dd 2.7 5.5 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors 4 intentionally blank 7 operation under these conditions is neither implied , nor guaranteed. 8 frequency select pins which have tri-level input 9 pci3/cfg0 is optional 10 if present. not all parts have this feature. operating supply current iamt mode current powerdown current input capacitance fall/rise time of all 3.3v control inputs from 20-8 0% notes on input/supply/common output dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 3 3.3v referenced inputs are: pci_stop#, cpu_stop#, t me, src5_en, itp_en, sclkl, sdata, testmode, testse l, ckpwrgd and cr# inputs if selected. 5 maximum vih is not to exceed vdd 6 human body model
7 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 p pm 2,4 clock period t period 48.00mhz output nominal 20.83125 20.83542 ns 2,3 absolute min/max period t abs 48.00mhz output nominal 20.48125 21.18542 ns 2 clk high time t high 8.216563 11.15198 v clk low time t low 7.816563 10.95198 v output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -29 ma v oh @max = 3.135 v -23 ma v ol @ min = 1.95 v 29 ma v ol @ max = 0.4 v 27 ma rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 2 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 2 output low current i ol output high current i oh electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 p pm 2, 4 clock period tperiod 14.318mhz output nominal 69.82033 69.86224 ns 2, 3 absolute min/max period tabs 14.318mhz output nominal 69.83400 70.84800 ns 2 clk high time thigh 29.97543 38.46654 v clk low time tlow 29.57543 38.26654 v output high voltage voh ioh = -1 ma 2.4 v output low voltage vol iol = 1 ma 0.4 v output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -33 -33 ma output low current iol vol @min = 1.95 v, vol @max = 0.4 v 30 38 ma rising edge slew rate tslr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate tflr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 55 % 2 jitter, cycle to cycle tjcyc-cyc vt = 1.5 v 1000 ps 2 1 edge rate in system is measured from 0.8v to 2.0v. 2 duty cycle, peroid and jitter are measured with res pect to 1.5v 3 the average period over any 1us period of time notes on se outputs: (unless otherwise noted, guara nteed by design and characterization, not 100% test ed in production). 4 using frequency counter with the measurment interva l equal or greater that 0.15s, target frequencies a re 14.318180 mhz, 33.333333mhz and 48.000000mhz clock jitter specs - low power differential outputs parameter symbol conditions min max units notes cpu jitter - cycle to cycle cpujc2c differential meas urement 85 ps 1 src jitter - cycle to cycle srcjc2c differential meas urement 125 ps 1,2 dot jitter - cycle to cycle dotjc2c differential meas urement 250 ps 1 1 jitter specs are specified as measured on a clock c haracterization board. system designers need to ta ke special care not to use these numbers, as the in -system performance will be somewhat degraded. the receive r emts (chispet or cpu) will have the rece 2 phase jitter requirement: the deisgnated ge2 outpu ts will meet the reference clock jitter requiremern ts from the pci express gen2 base spec. the test is performed on a componnet test board under quiet condittions with a ll outputs on. jitter analysis is performed using a standardized tool provided by the pci sig or equi valent. measurement methodology is as defined by the pci sig. notes on dif output jitter: (unless otherwise noted , guaranteed by design and characterization, not 10 0% tested in production).
8 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 pin 14 spread mhz % 0 0 0 0 n/a n/a n/a 0 0 0 1 n/a n/a n/a 0 0 1 0 n/a n/a n/a 0 0 1 1 n/a n/a n/a 0 1 0 0 n/a n/a n/a 0 1 0 1 n/a n/a n/a 0 1 1 0 n/a n/a n/a 0 1 1 1 n/a n/a n/a 1 0 0 0 n/a n/a n/a 1 0 0 1 n/a n/a n/a 1 0 1 0 n/a n/a n/a 1 0 1 1 n/a n/a n/a 1 1 0 0 25.000 none 25mhz on se1 1 1 0 1 n/a n/a n/a 1 1 1 0 n/a n/a n/a 1 1 1 1 n/a n/a n/a comment b1b1 b1b4 b1b3 b1b2 table 2: pll3 quick configuration (read only) table 3: vswing select table b9b2 b9b1 b9b0 vswing 0 0 0 0.3v 0 0 1 0.4v 0 1 0 0.5v 0 1 1 0.6v 1 0 0 0.7v 1 0 1 0.8v 1 1 0 0.9v 1 1 1 1.0v table 4: device id table 0 1 1 0 48 ssop/tssop b8b6 b8b5 b8b4 comment b8b7
9 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 pci_stop# power management smbus oe bit pci_stop# stoppable free running stoppable free running 1 running running running running 0 low running ck= high ck# = low running disable x cpu_stop# power management smbus oe bit stoppable free running 1 running running 0 ck= high ck# = low running disable x cr# power management smbus oe bit cr# cr# controlled free running 1 running running 0 disable x pd# power management device state w/o latched input w/latched input latches open low power down 25mhz m1 25mhz virtual power cycle to latches open 25mhz cpu1 ck= pull down, ck# = low ck= pull down, ck# = low ck= pull down, ck# = low running ck= pull down ck# = low enable ck= pull down, ck# = low ck= pull down, ck# = low low hi-z single-ended clocks (except se1) ck= pull down ck# = low ck= pull down ck# = low low se1 w/b11b5 = 0 enable ck= pull down, ck# = low low cpu_stop# enable single-ended clocks differential clocks (except cpu) low ck = pull down, ck# = low cpu clocks differential clocks (except cpu) se1 w/b11b5 = 1 differential clocks (except cpu1)
10 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 general smbus serial interface information for the ics9lprs535 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read:? controller (host) will send star t bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining bytelocation = n ? ics clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
11 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 byte 0 fs readback and pll selection register bit pin name description type 0 1 default 7 - fslc cpu freq. sel. bit (most significant) r latch 6 - fslb cpu freq. sel. bit r latch 5 - fsla cpu freq. sel. bit (least significant) r latch 4 - iamt_en set via smbus or dynamically by ck505 if detects dynamic m1 rw legacy mode iamt enabled 0 3 reserved reserved rw 0 2 - src_main_sel select source for src main r src main = pll1 src main = pll3 0 1 - sata_sel select source for sata clock rw sata = src_main sata = pll2 0 0 - pd_restore 1 = on power down de-assert return to last known st ate 0 = clear all smbus configurations as if cold power -on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 dot96 select and pll3 quick config register bit pin name description type 0 1 default 7 13/14 src0_sel select src0 or dot96 rw src0 dot96 0 6 - pll1_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 5 reserved reserved rw 1 4 pll3_cf3 pll3 quick config bit 3 r 1 3 pll3_cf2 pll3 quick config bit 2 r 1 2 pll3_cf1 pll3 quick config bit 1 r 0 1 pll3_cf0 pll3 quick config bit 0 r 0 0 pci_sel pci_sel r pci from pll1 pci from src_main 1 byte 2 output enable register bit pin name description type 0 1 default 7 ref_oe output enable for ref, if disabled output is tri-stated rw output disabled output enabled 1 6 usb_oe output enable for usb rw output disabled output enabled 1 5 pcif5_oe output enable for pci5 rw output disabled out put enabled 1 4 pci4_oe output enable for pci4 rw output disabled output enabled 1 3 reserved reserved rw 1 2 reserved reserved rw 1 1 reserved reserved rw 1 0 pci0_oe output enable for pci0 rw output disabled outp ut enabled 1 byte 3 output enable register bit pin name description type 0 1 default 7 reserved reserved rw 1 6 reserved reserved rw 1 5 reserved reserved rw 1 4 src8/itp_oe output enable for src8 or itp rw output d isabled output enabled 1 3 src7_oe output enable for src7 rw output disabled outp ut enabled 1 2 reserved reserved rw 1 1 src5_oe output enable for src5 rw output disabled output enabled 1 0 src4_oe output enable for src4 rw output disabled outp ut enabled 1 25mhz from pll3 quick config see table 1 : cpu frequency select table
12 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 byte 4 output enable and spread spectrum disable re gister bit pin name description type 0 1 default 7 src3_oe output enable for src3 rw output disabled outp ut enabled 1 6 sata/src2_oe output enable for sata/src2 rw output di sabled output enabled 1 5 reserved reserved rw 0 4 src0/dot96_oe output enable for src0/dot96 rw output disabled output enabled 1 3 cpu1_oe output enable for cpu1 rw output disabled outp ut enabled 1 2 cpu0_oe output enable for cpu0 rw output disabled outp ut enabled 1 1 pll1_ssc_on enable pll1's spread modulation rw spread disabled spread enabled 1 0 reserved reserved rw 0 byte 5 clock request enable/configuration register bit pin name description type 0 1 default 7 cr#_a_en enable cr#_a (clk req), pci0_oe must be = 1 for this bit to take effect rw disable cr#_a enable cr#_a 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw cr#_a -> src0 cr#_a -> src2 0 5 reserved reserved rw 0 4 reserved reserved rw 0 3 cr#_c_en enable cr#_c (clk req) rw disable cr#_c enabl e cr#_c 0 2 cr#_c_sel sets cr#_c -> src0 or src2 rw cr#_c -> src0 cr#_c -> src2 0 1 cr#_d_en enable cr#_d (clk req) rw disable cr#_d enable cr#_d 0 0 cr#_d_sel sets cr#_d -> src1 or src4 rw na, src1 not present cr#_d -> src4 0 byte 6 clock request enable/configuration and stop control register bit pin name description type 0 1 default 7 reserved reserved rw 0 6 cr#_f_en enable cr#_f (clk req) -> src8 rw disable cr #_f enable cr#_f 0 5 reserved reserved rw 0 4 reserved reserved rw 0 3 reserved reserved rw 0 2 reserved reserved rw 0 1 reserved reserved rw 0 0 src_stp_crtl if set, srcs (except src1) stop with p ci_stop# rw free running stops with pci_stop# assertion 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 ics is 0001 b rev = 0001 c rev = 0010 vendor id ics is 0001, binary revision id rev b = 0001 rev c = 0010
13 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 byte 8 device id and output enable register bit pin name description type 0 1 default 7 device_id3 r 0 6 device_id2 r 1 5 device_id1 r 1 4 device_id0 r 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 se1_oe output enable for se1 rw disabled enabled 1 0 reserved reserved rw - - 0 byte 9 output control register bit pin name description type 0 1 default 7 pcif5 stop en allows control of pcif5 with assertio n of pci_stop# rw free running stops with pci_stop# assertion 0 6 tme_readback truested mode enable (tme) strap status r normal operation no overclocking 0 5 ref strength sets the ref output drive strength rw 1x (2loads) 2x (3 loads) 1 4 test mode select allows test select, ignores ref/fsc/testsel rw outputs hi-z outputs = ref/n 0 3 test mode entry allows entry into test mode, ignores fsb/testmode rw normal operation test mode 0 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io output voltage select rw 0 0 io_vout0 io output voltage select (least significan t bit) rw 1 byte 10 stop enable register bit pin name description type 0 1 default 7 src5_en readback readback of src5 enable latch r cpu/pci stop enabled src5 enabled latch 6 reserved rw tbd tbd 0 5 reserved rw tbd tbd 0 4 reserved rw tbd tbd 0 3 reserved rw tbd tbd 0 2 reserved rw tbd tbd 0 1 cpu 1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu 0 stop enable enables control of cpu 0 with cpu _stop# rw free running stoppable 1 byte 11 iamt enable register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 wol_stop_en enable 25mhz wlan clock during m1 or power down. this bit is sticky 1. rw 25mhz disabled in powerdown or m1 25mhz enabled in powerdown or m1 note 4 reserved reserved rw - - 1 3 cpu2_amt_en m1 mode clk enable, only if itp_en=1 rw disable enable 0 2 cpu1_amt_en m1 mode clk enable rw disable enable 1 1 pci-e_gen2 determines if pci-e gen2 compliant r non-gen2 pci-e gen2 compliant 1 0 cpu 2 stop enable enables control of cpu 2 (itp)with cpu_stop# rw free running stoppable 1 note rev b device default is 0. rev c device is 1 byte 12 byte count register bit pin name description type 0 1 default 7 reserved rw 0 6 reserved rw 0 5 bc5 rw 0 4 bc4 rw 0 3 bc3 rw 1 2 bc2 rw 1 1 bc1 rw 0 0 bc0 rw 1 read back byte count register, max bytes = 32 reserved table of device identifier codes, used for differentiating between ck505 package options, etc. see device id table see table 3: v_io selection (default is 0.8v) byte count is 13 decimal.
14 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 test clarification table comments fslc/ test_sel hw pin fslb/ test_mod e hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal opera tion) b9b4: 1= ref/n, default = 0 (hi-z) hw sw power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if power-up w/ v>2.0v then use test_sel if power-up w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
15 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a 0 8 0 8 variations min max min max 48 15.75 16.00 .620 .630 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations
16 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 indexarea 1 2 n d e1 e a seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 de e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (2 0 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publicat ion 95, m o-153 ordering information part / order number shipping packaging package tempera ture wake-on lan default 9lprs535bflf tubes 48-pin ssop 0 to +70c 9lprs535bflft tape and reel 48-pin ssop 0 to +70c 9lprs535bglf tubes 48-pin tssop 0 to +70c 9lprs535bglft tape and reel 48-pin tssop 0 to +70c 9lprs535cflf tubes 48-pin ssop 0 to +70c 9lprs535cflft tape and reel 48-pin ssop 0 to +70c 9lprs535cglf tubes 48-pin tssop 0 to +70c 9lprs535cglft tape and reel 48-pin tssop 0 to +70c disabled enabled
17 integratedcircuit systems, inc. ics9lprs535 datasheet 1461a?07/28/09 revision history rev. issue date description page # 0.1 3/10/2008 1. intial release 0.2 4/23/2008 1. updated smbus, front page, block dia gram and deleted page 5 1, 4, 12-13 0.3 5/7/2008 1. corrected typo in cpu power management table. w rong column heading 2. corrected typo in pd# power management table se1 should be low when b11b5 = 0 3. corrected byte 5 bit 0 to be na when set to 0. src1 is not present. 4. byte 6, bit 6 restored. cr_f# is present and ca n control src8 various 0.4 7/7/2008 1. corrected power management table to remove the s top mode drive bits, which do not exist in this device. 2. updated differential clock period table. various 0.5 7/10/2008 1. updated pin names to reflect lpr output type. p in descriptions updated too. 2. smbus updated to indicate pcie gen2 status various 0.6 7/13/2009 1. removed references to cr# inputs that do not exi st in this part. 2. clarified functionality of byte 11, bit 5. various 0.7 7/21/2009 1. lowered idd values to reflect perfor mance of the device. a 7/28/2009 1. moved to final 2. added "wake-on lan default" parameter to orderin g info table.

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